1. Field of Invention
This invention relates to memory systems, and more particularly to non-volatile semiconductor memory devices employed to store bootstrap or xe2x80x9cbootxe2x80x9d code in a computer system.
2. Description of Related Art
Computer systems typically include hardware dependent software which must be valid when electrical power is applied to the systems. Such software includes instructions which initialize system hardware components (e.g., interrupt controller, direct memory access controller, and serial port) and provide a basic input and output system (BIOS). The BIOS provides an interface between system software and hardware (e.g., core logic chip set, graphics controller, keyboard, and disk drives). Computer system software programs typically access system hardware components using the BIOS.
A typical computer system includes a microprocessor which functions as a central processing unit (CPU). The microprocessor executes instructions stored within a main memory. The main memory typically includes a non-volatile read only memory (ROM) portion and a volatile random access memory (RAM) portion. Only the contents of the ROM portion of the main memory are valid at system power up, and thus the BIOS software is stored within the ROM portion of main memory. When power is applied to the microprocessor, or a RESET signal is asserted, the microprocessor begins fetching and executing instructions at a predetermined location within the main memory. Thus the ROM portion of the main memory includes the memory location where the microprocessor begins fetching and executing instructions. For example, many modem computer systems include x86 microprocessors. When power is applied to an x86 microprocessor, or when the RESET signal is asserted, the x86 microprocessor begins fetching and executing instructions located at the highest possible address in main memory. In such systems, the ROM portion of the main memory is mapped to the uppermost addresses of the main memory.
The BIOS code typically contains bootstrap or xe2x80x9cbootxe2x80x9d code, which typically constitutes a minimal amount of code necessary to initialize the computer system. The boot code typically verifies the integrity of the BIOS code, checks the functionality of the RAM portion of the main memory, and begins the process of copying operating system software from disk (e.g., floppy disk or hard disk) to the RAM portion of the main memory. Once initialized, the computer system executes programs stored in the RAM portion of the main memory.
BIOS code is often stored within various types of non-volatile ROM devices, including programmable read-only memory (PROM) devices, erasable programmable read only memory (EPROM) devices, and electrically erasable programmable read only memory (EEPROM) devices. EPROM and EEPROM memory devices include floating-gate metal oxide semiconductor (MOS) transistors programmed by adding or removing charge from the floating gate. PROM, EPROM, and EEPROM devices are all programmed electrically. PROM devices typically include fusible links which are xe2x80x9cblownxe2x80x9d during programming. PROM devices may thus be programmed only once. Programmed EPROM and EEPROM devices, on the other hand, may be erased and reprogrammed. EPROM elements are erased by exposure to ultraviolet (UV) radiation, while EEPROM elements are erased electrically.
In order to take full advantage of sophisticated system hardware components becoming increasingly available, existing BIOS code must often be modified. Unfortunately, the more common ROM devices used to store BIOS software must either be replaced (PROM) or removed from a computer system and reprogrammed in order to be upgraded (EPROM and EEPROM).
Flash memory devices, sometimes called flash EEPROM devices, are rapidly replacing ROM devices in BIOS applications. Like EPROM and EEPROM memory devices, flash memory devices include floating-gate metal oxide semiconductor (MOS) transistors programmed by adding or removing charge from the floating gate, thus providing non-volatile storage. Unlike EPROM and EEPROM devices, however, flash memory devices may be reprogrammed while still in the computer system.
Flash memory devices are typically divided into sections or blocks, and all storage locations within a given block may be electrically erased simultaneously. Auxiliary circuitry is required to manage the erase blocks, and the size and complexity of the auxiliary circuitry increases with the number of erase blocks. Erase block size is often a compromise between cost, which increases with the number of erase blocks, and performance, which decreases with increasing erase block size. A single erase block of a flash memory device is often dedicated to boot code storage. As computer systems cannot operate without boot code, such xe2x80x9cboot blocksxe2x80x9d are typically protected from erasure by software and/or hardware mechanisms. To a typical user, a boot block is essentially a read-only portion of an otherwise read-write memory unit.
While the number of memory locations required to store boot code varies from computer system to computer system, boot block sizes are typically fixed (e.g., 16 kilobytes or 16 Kbytes). In many systems, the boot code occupies only a small portion of the boot block. As the boot block is protected from erasure, the unused portion of the boot block cannot be used by system software for data storage and retrieval. As a result, a large portion of the boot block goes unused in such systems. It would thus be beneficial to have a flash memory device wherein the size of the protected portion used to store the boot code may be programmably selected.
The problems outlined above are in large part solved by a non-volatile memory system having a section dedicated for storage of instructions and data used to initialize a central processing unit (i.e., boot code), wherein the size of the boot code section may be programmably selected. The non-volatile memory system of the present invention includes a memory array configured to store data and having a boot code section for boot code storage. The contents of a programmable storage unit (e.g., a portion of a programmable register) determine the number of memory locations within the boot code section (i.e., the size of the boot code section).
One embodiment of the non-volatile memory system includes the memory array, a logic unit, a control unit, and a program store. The memory array includes multiple non-volatile memory cells (e.g., flash EEPROM cells). The memory cells are divided into memory blocks of equal size. All of the memory cells within a given memory block may be erased simultaneously. A number of the memory blocks are allocated for boot code storage, forming the boot code section of the memory array. The control unit is coupled to the memory array, and controls storage of data within and retrieval of data from the memory array. The control unit includes a command register and a configuration register. The command register is used to store one or more commands issued to the non-volatile memory system. The configuration register includes a boot code section size field. The contents of the boot code section size field determine the number of memory blocks making up the boot code section of the memory array. The logic unit is coupled between the control unit and the memory array, and is coupled to receive address, data, and control signals from an external source. The logic unit is configured to provide the address, data, and control signals to the control unit and to the memory array. The program store stores instructions and data which determine the functionality of the control unit.
Commands and configuration data are conveyed from an external source to the non-volatile memory system using predetermined sequences of bus write cycles. The control unit receives the commands and stores the commands within the command register. The control unit also receives configuration data and stores the configuration data within the configuration register. The contents of the command register and the configuration register determine the operation of the control unit.
One embodiment of a computer system of the present invention includes a central processing unit (CPU), and expansion bus, a memory bus, chip set logic, and the non-volatile memory system. The CPU is configured to execute instructions, preferably x86 instructions. The expansion bus is adapted for coupling to one or more peripheral devices. The non-volatile memory unit is coupled to the memory bus. The chip set logic is coupled to the CPU, the expansion bus, and the memory bus. The chip set logic functions as interface between the CPU and the expansion bus, and between the CPU and the non-volatile memory system.